Data Logger

Pardis Data Logger is a very useful device for test and verification of digital implemented circuits. using a common interface, a wide input bus can be attached to the device in its own clock rate and logging is performed with a manual or automatic trigger signal. In addition, user defined input pattern can also in deceive and applied to the hardware simultaneously. Typical support clock rates between 70-100 MHZ in 25 or 44-bit busses depending on the quality of the hardware output buffer.
Logged data is transferred to a PC using a high-speed USB 2.0 interface with a typical rate of 100-200 Mbps. This efficient interface enables logging and read-back of a huge amount of data in a few seconds. This data can then be logged for comparison or any other user defined process.
Powerful software is developed to control the logging and read-back processes and for pre-processing of logged data.

Main Board  
  • Xilinx XC2VP7 or XC2VP4FPGA used for hardware core

  • Tow 2x25 IDC Connectors used for hardware interface

  • One 2x25 IDC connectors used for USB 2.0 interface

  • Tow Oscillators, two push buttons and 4 dip switches used

  • SODIMM SDRAM modules could be installed on the board

  • USB 2.0 interface could be used in other designs

     data logger core: 

  • Stream high-speed data logging with its own clock and trigger

  • 70-100HZ typical logging speed

  • 1 to 48-bit data logging and read-back


  • User-friendly GUI interface for device operation

  • Pre-processing software for graphic data verification

     Clock Source:

  • SMA

  • Pin Header

  • Fixed Oscillator (40 MHz) and its Divisions

  • Variable Oscillator its Divisions

     Data Width:

  • 16 Bits

  • 32 Bits

  • 48 Bits

     Process Control:

  • Automatic (Software-based)

  • Manual

     Operation Mode:

  • Normal logging

  • Cyclic Logging

  • Test Pattern Logging


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